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The roadmap of microelectronics is focused on progress along the Moore’s law curve. In Photonics we expect a different development. It will start with commercial application of ASPICs with a complexity in the range of 5-50 components in rather basic generic foundry processes. The next step will be an increase in performance and capabilities of the generic processes, e.g. with respect to speed, power consumption and number of basic building blocks supported, which may lead to some increase in the complexity of the chips, but not dramatic. Once the foundry processes cover a wide range of applications, their steady performance improvement will allow for designing increasingly complex chips.

It seems unlikely that the complexity supported by the generic processes, as described here and developed by EuroPIC, will exceed a component count of 1000 for a number of reasons. First, SOAs and lasers typically have a power dissipation of several 100mW. So their number is typically restricted to several tens up to a maximum of a few hundreds, because of heat sinking limitations. Secondly, although they often carry digitally modulated signals, the basic building blocks and the circuits built from them essentially operate in an analogue mode, which means that on passing a number of components the signal will accumulate noise and distortion and need to be regenerated. Regenerators can be integrated too, but they consume space and power.

Finally, from the point of view of functionality it is difficult at the moment to imagine what circuits would need more than a thousand components. WDM devices might go up to one hundred channels, but in order to arrive at one thousand components they would need 10 components per channel, which looks rather high; what should they do? For devices without a huge parallelism it is even more difficult to think of such large circuits.

The final outcome of the EuroPIC programme will be to have carried out two trial runs of the new generic foundry process. Partners Oclaro Technology plc in the UK, and the Fraunhofer Inst. for Telecommunications Heinrich Hertz Institute in Germany will each establish their own generic process. Processes which at this stage will have different strengths but may well converge in capability in the future. To ensure that these are real tests against real market requirements, EuroPIC is working closely with applications orientated groups within the project. The first trials will proceed with PIC designs supplied by applications partners in the consortium, and aim to test out the generic process from end to end for the first time. They will reveal any major unforeseen problems. The second run starting mid 2011 will properly demonstrate the technical feasibility of the generic approach and resolve the issues which have arisen in the initial trials.

It is by working through such programmes as EuroPIC and the Dutch national programme MEMPHIS (on the development of an industrial generic foundry capability, including software design toolkits for fast and accurate chip design, and generic packaging and test facilities, that commercial, self-sustaining photonic foundry operation might be achieved. Through EuroPIC, restricted access to alpha and then beta platform releases may begin as early as 2011.