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Research Challenges for EuroPIC

The fundamental concept within EuroPIC is that of the generic process as applied to InP-based PICs. This is a radical departure from current practice because a generic process, by definition, is application-blind in that it should be capable of producing any circuit design providing the design lies within certain defined boundaries. In such a generic process there would no longer be the requirement for technologists to hand-craft processes to deliver PICs to a specific design which is the normal practice in the research literature (and indeed in industrial R&D) today, and which inevitably leads towards high development and production costs. A true generic process for InP PICs does not currently exist anywhere in the world and there are very significant challenges which must be overcome to achieve it. These will require research to achieve advances in the state-of-the-art on several levels:

• technology research on materials processing in the InP semiconductor system and its alloys InGasAsP and InGaAlAs.
• technology research at the basic building block level to ensure maturity and assess tolerance windows
• research on process integration
• research on supply chain integration

In EuroPIC there is considerable novelty in the chip designs themselves, many of which have not been made before, and we expect that the PICs that result will in themselves be state-of-the-art in terms of performance and complexity.

The EuroPIC philosophy is based on the belief that we can evolve from existing InP-based building blocks to a generic process by making strategic advances on technology that is available today and by developing new ways of combining functionality on a chip. Rather than pursuing small incremental technology steps, we will adopt the more challenging approach of parallel research by providing a working platform as a test bed, while working to define the shape of the platform to come.

Research on material processing

Research into new processes in any field of scientific endeavour is a complex and challenging task. In a relatively mature field such as InP based photonics past experience has shown that issues often arise from rather subtle interactions between different process stages: the difference between devices fabricated on semi-insulating substrates and doped substrates, for example, which is now compounded by the presence of other building blocks on the same chip, and in crystallographic constraints on layout and device orientation which may mean that conventional design choices are incompatible. There are also known challenges to be met in processes which make use of new material combinations such as AlGaInAs:InP (e.g. preventing Al oxidation), and in previously unanticipated device configurations.

Research on building block maturity

Short turn-around times for a trajectory from concept to scalable production requires mature and reliable building blocks with established design windows for the degrees of freedom available to designers. Reducing the performance specifications is; however, not an option – in most cases high performance is needed to create commercially viable products. Investigation of trade-offs between performance and the generality of the platform are therefore important research topics.

Research on process Integration

Through technology convergence driven by commercial pressures in application markets we expect the generic platforms supported by different fabs to evolve (converge) in the long term to look quite similar to the external observer, much like the position in silicon IC processing today. Generic foundry processes and packaging require a long-term roadmap in which added technology capabilities are matched by suitable cost models.

Research on supply chain integration

The generic fab requires a fresh look at the whole process chain from concept to packaged chip. Many of the elements in the chain are currently missing and must be created. For example, novel software design methods and tools are required at the circuit level and the generic fab process itself needs to be developed along with complementary generic packaging approaches. Very often in the past, packaging has been left as an afterthought. In EuroPIC, chip “packageability” will be designed in from the start. To remedy all of these deficiencies is beyond the scope of a single programme but we can address enough of them to be confident that a commercial release of the first generic InP foundry process will be achievable.